Module Catalogues, Xi'an Jiaotong-Liverpool University   
 
Module Code: EEE339
Module Title: Digital System Design with HDL
Module Level: Level 3
Module Credits: 5.00
Academic Year: 2017/18
Semester: SEM1
Originating Department: Electrical and Electronic Engineering
Pre-requisites: EEE104 EEE205 EEE216
   
Aims
To provide students with the ability to:
- Design and synthesise digital systems using HDL.
- Understand the problems of meta-stability in digital systems.
- Design and synthesise microsprocessor systems using HDL
- Develop and test System on a Programmable Chips (SOPC) design using Altera NIOS
Learning outcomes 
Students completing the module successfully should:
(note: for accreditation and other reasons, sub-headings could be added apart from the items below by departments)



A Knowledge and Understanding

On successful completion of the module the student is expected to havebe able to:

 Uunderstanding of issues involving digital synthesis (e.g. the capabilities of the HDL language for synthesis and simulation);.

 Knowledge of the capabilities of the HDL language for synthesis.

 Understanding understandof the potential pitfalls caused my by meta-stability;.

 Knowledge ofuse the Library of Parameterised Modules (LPM)

 Knowledge of the capabilities of the HDL language for simulation.

 Uunderstanding of the design issues when generating complex digital systems (including microprocessors);.

 Knowledge ofunderstand the capabilities of SOPC designs.


B Intellectual Abilities

On successful completion of the module, students should be able to demonstrate ability in applying knowledge of the module topics to

 sSynthesise, using HDL, a stable and robust digital system.

 Simulate simulate and sSynthesise a RISC microprocessor

 iImplement a SOPC design


C Practical Skills

On successful completion of the module, students should be able to show experience and enhancement of the following discipline-specific practical skills:

Use of CAE tools for designing, synthesising and simulating digital systems.


D General Transferable Skills

On successful completion of the module, students should be able to show experience and enhancement of the following key skills:

 Independent learning.

 Problem solving and design skills.


Method of teaching and learning 
This module will be delivered through a combination of formal lectures, tutorials and both supervised and unsupervised laboratory sessions.
Syllabus 
Chapter 1 Introduction
outline the philosophy of the module and introduce the capabilities of the Altera NIOS board on which the assignments are based.


Chapter 2 Revision of ASM design techniques


Chapter 3 Combinational Logic Synthesis with HDL

Introduces the basic syntax of HDL and how to synthesise combinational circuits.


Chapter 4 Sequential Logic Synthesis with HDL

Introduces how to synthesise sequential circuits and State Machines.


Case Study 1 Detailed digital design example


Chapter 5 System Synthesis with HDL

Introduces how to combine modules to synthesis full systems.


Chapter 6 Metastability

Introduces the concept of metastability, explains how to predict the frequency of occurrence and introduces techniques to reduce the likelihood of implementing designs with metastable hazards.


Chapter 7 The Library of Parameterised Modules (LPM) and the Electronic Design Interchange Format (EDIF) for digital system synthesis.


Case study 2 Detailed digital design example


Chapter 8 Microprocessor Synthesis - describes the uP1 core and how to synthesise a simple microprocessor.


Chapter 9 Outlines the performance requirements of processors i.e. assessment of performance based on clock speed, no of clock cycles per instruction etc.


Chapter 10 Describes the functionality of a MIPS Single Cycle Processor in terms of data paths.


Chapter 11 Introduces a control unit for the MIPS Single Cycle Processor.


Chapter 12 Describes the synthesis and simulation of the MIPS processor in the Quartus Environment and introduces the first assignment.


Chapter 13 Describes the architecture requirements for a Multi-cycle variant of the MIPS processor.


Chapter 14 Introduces a control unit for the MIPS Multi Cycle Processor.


Delivery Hours  
Lectures Seminars Tutorials Lab/Prcaticals Fieldwork / Placement Other(Private study) Total
Hours/Semester 26       48    76  150 

Assessment

Sequence Method % of Final Mark
1 Assignment 1 15.00
2 Assignment 2 15.00
3 Final Exam 70.00

Module Catalogue generated from SITS CUT-OFF: 10/22/2017 10:42:59 AM