Module Catalogues, Xi'an Jiaotong-Liverpool University   
 
Module Code: EEE339
Module Title: Digital System Design with HDL
Module Level: Level 3
Module Credits: 5.00
Academic Year: 2018/19
Semester: SEM1
Originating Department: Electrical and Electronic Engineering
Pre-requisites: EEE104 AND EEE205 AND EEE216 EEE205 EEE104
   
Aims
To provide students with the ability to:
- Design and synthesise digital systems using HDL.
- Understand the problems of meta-stability in digital systems.
- Design and synthesise microsprocessor systems using HDL
- Develop and test System on a Programmable Chips (SOPC) design using Altera NIOS
Learning outcomes 
A. Acquire the knowledge of the HDL language for synthesis, the use of the Library of Parameterised Modules (LPM) and the capabilities of the HDL language for simulation.

B. Understand the design issues when generating complex digital systems (including microprocessors).

C. Apply the knowledge of the module topics to the synthesis of a stable and robust digital system using HDL in order to simulate and synthesise a RISC microprocessor, and implement a SOPC design.

D. Obtain the experience and practical skills in the use of CAE tools for designing, synthesising and simulating digital systems.


Method of teaching and learning 
This module will be delivered through a combination of formal lectures, tutorials and both supervised and unsupervised laboratory sessions.
Syllabus 
Chapter 1 Introduction
outline the philosophy of the module and introduce the capabilities of the Altera NIOS board on which the assignments are based.


Chapter 2 Revision of ASM design techniques


Chapter 3 Combinational Logic Synthesis with HDL

Introduces the basic syntax of HDL and how to synthesise combinational circuits.


Chapter 4 Sequential Logic Synthesis with HDL

Introduces how to synthesise sequential circuits and State Machines.


Case Study 1 Detailed digital design example


Chapter 5 System Synthesis with HDL

Introduces how to combine modules to synthesis full systems.


Chapter 6 Metastability

Introduces the concept of metastability, explains how to predict the frequency of occurrence and introduces techniques to reduce the likelihood of implementing designs with metastable hazards.


Chapter 7 The Library of Parameterised Modules (LPM) and the Electronic Design Interchange Format (EDIF) for digital system synthesis.


Case study 2 Detailed digital design example


Chapter 8 Microprocessor Synthesis - describes the uP1 core and how to synthesise a simple microprocessor.


Chapter 9 Outlines the performance requirements of processors i.e. assessment of performance based on clock speed, no of clock cycles per instruction etc.


Chapter 10 Describes the functionality of a MIPS Single Cycle Processor in terms of data paths.


Chapter 11 Introduces a control unit for the MIPS Single Cycle Processor.


Chapter 12 Describes the synthesis and simulation of the MIPS processor in the Quartus Environment and introduces the first assignment.


Chapter 13 Describes the architecture requirements for a Multi-cycle variant of the MIPS processor.


Chapter 14 Introduces a control unit for the MIPS Multi Cycle Processor.


Delivery Hours  
Lectures Seminars Tutorials Lab/Prcaticals Fieldwork / Placement Other(Private study) Total
Hours/Semester 26      48    75  150 

Assessment

Sequence Method % of Final Mark
1 Assignment 1 15.00
2 Assignment 2 15.00
3 Final Exam 70.00

Module Catalogue generated from SITS CUT-OFF: 5/22/2018 9:52:36 PM