Module Catalogues, Xi'an Jiaotong-Liverpool University   
 
Module Code: EEE310
Module Title: Embedded Computer Systems
Module Level: Level 3
Module Credits: 2.50
Academic Year: 2017/18
Semester: SEM2
Originating Department: Electrical and Electronic Engineering
Pre-requisites: N/A
   
Aims
To obtain an understanding of the construction and operation of embedded computer systems and their components.
Furthermore to gain an understanding of how computer performance is dependent upon the design of computer architectures and sub-circuits.
Learning outcomes 
Knowledge and Understanding

After successful completion of the module, the student should have:

An understanding of the internal operation of a CPU Knowledge of some methods used to increase CPU performance

An understanding of the difference between RISC and CISC type systems

A knowledge of memory systems


Intellectual Abilities

On successful completion of the module the student should be able to understand published data concerning use of typical computer system components.


Practical Skills

After successful completion of the module students should be able to determine how any computer system functions from published data and be able to apply this to developing simple processor systems from large scale modules.


General Transferable Skills

On successful completion of the module, students should be able to show experience and enhancement of the following key skills:

Independent learning

Problem solving and design skills
Method of teaching and learning 
This module will be delivered through a combination of formal lectures, problem classes and case studies.
Coursework is not normally anonymously marked as staff wish to provide meaningful feedback.
Syllabus 
Lecture 1 Characteristics of Embedded Systems.

Low power, design reuse, open standards, IP


Lectures 2 - 5 Computer Architecture

von Neumann structure, standard CPU architecture, characteristics and comparison of CISC and RISC systems


Lectures 6 - 9 ALU architecture

requirements of the ALU, number representation, ALU subcircuits


Lectures 10 - 12 Memory cache

performance measures, direct mapped, associative cache design, write strategies

Lectures 13 - 15 Thumb instruction set

characteristics, performance benefits


Lectures 16 - 18 Arithmetic logic unit Adder, barrel shifter, multiplier

Delivery Hours  
Lectures Seminars Tutorials Lab/Prcaticals Fieldwork / Placement Other(Private study) Total
Hours/Semester 24           51  75 

Assessment

Sequence Method % of Final Mark
1 Final Exam 90.00
2 Course Work 10.00

Module Catalogue generated from SITS CUT-OFF: 10/22/2017 9:33:00 PM