Module Catalogues, Xi'an Jiaotong-Liverpool University   
 
Module Code: EEE205
Module Title: Digital Electronics II
Module Level: Level 2
Module Credits: 2.50
Academic Year: 2017/18
Semester: SEM1
Originating Department: Electrical and Electronic Engineering
Pre-requisites: EEE104
   
Aims
To provide students with the ability to:

Design digital systems using the Algorithmic State Machine (ASM) methodology.

Understand the features of Programmable Logic Devices (PLDs) and use them in their designs.

Interface memory and other peripherals to microprocessor systems.
Learning outcomes 
Knowledge and Understanding

On successful completion of the module, students should be able to demonstrate: Knowledge of the Algorithmic State Machine (ASM) design technique.

Knowledge of the capabilities of synchronous digital systems.

Knowledge of the capabilities of FPGAs.

Understanding of the requirements of interfacing memory and peripherals to microprocessor systems.


Intellectual Abilities

On successful completion of the module, students should be able to demonstrate ability in applying knowledge of the above topics to

Design a stable and robust digital system.

Implementing the digital system in an FPGA.


Practical Skills

On successful completion of the module, students should be able to show experience and enhancement of the following discipline-specific practical skills:

Use of CAE tools for designing and simulating digital systems.


General Transferable Skills

On successful completion of the module, students should be able to show experience and enhancement of the following key skills:

Independent learning.

Problem solving and design skills
Method of teaching and learning 
This module will be delivered through a combination of formal lectures, tutorials and both supervised and unsupervised laboratory sessions.
Syllabus 
Chapter 1 Revision of simple combinational and sequential circuits

This will provide a brief review of the year 2 EE10312 Digital Electronics (I) course

Chapter 2 Algorithmic State Machines (ASMs)

The notation for designing ASMs will be introduced along with methods for translating ASM designs into hardware including the traditional technique and the “one-hot” method.

Potential pitfalls in designs will be covered along with some case studies.

Chapter 3 Programmable Logics Devices (PLDs)

Features of EPROMs, PALs and PALs will be covered along with an explanation of how they can implement sequential systems.

The 22V10 device will be covered in detail along with products from the Altera Family.

Chapter 4 Hardware Design Languages (HDLs)

The concept of Hardware design languages will be introduced with emphasis being placed on AHDL although a short introduction to VHDL will be presented.

Chapter 5 Large combinational and sequential circuits

Problems encountered when the specification for a combinational logic circuit is such that the resulting circuit would be very large.

Methods for design of large combinational or sequential logic circuits and some of the problems associated with such circuits will be introduced along with the Quine-McCluskey method for Boolean minimisation.

Chapter 6 Processor interface circuits

Logic requirements, decoders, timing specifications and electrical requirements for interfacing digital systems to microprocessors and microcontrollers.
Delivery Hours  
Lectures Seminars Tutorials Lab/Prcaticals Fieldwork / Placement Other(Private study) Total
Hours/Semester 22     6  6    41  75 

Assessment

Sequence Method % of Final Mark
1 Formal Exam 70.00
2 Laboratory 10.00
3 Assignments 1 3.00
4 Mid-Term Test 10.00
5 Assignments 2 3.00
6 Assignments 3 4.00

Module Catalogue generated from SITS CUT-OFF: 10/22/2017 9:26:58 PM